PIC18FXX20 Datasheet, PDF (54/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
TABLE 4-3: REGISTER FILE SUMMARY
File Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 32, 42
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 32, 42
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 32, 42
STKPTR
STKFUL STKUNF
—
Return Stack Pointer
00-0 0000 32, 43
PCLATU
—
—
bit21 Holding Register for PC<20:16>
--10 0000 32, 44
PCLATH Holding Register for PC<15:8>
0000 0000 32, 44
PCL
TBLPTRU
PC Low Byte (PC<7:0>)
—
—
bit21⁽²⁾
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
0000 0000 32, 44
--00 0000 32, 64
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 32, 64
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 32, 64
TABLAT Program Memory Table Latch
0000 0000 32, 64
PRODH Product Register High Byte
xxxx xxxx 32, 85
PRODL
Product Register Low Byte
xxxx xxxx 32, 85
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF 0000 0000 32, 89
INTCON2
RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP
RBIP 1111 1111 32, 90
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF 1100 0000 32, 91
INDF0
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
n/a
57
POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented
(not a physical register)
n/a
57
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented
(not a physical register)
n/a
57
PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) n/a
57
PLUSW0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented
(not a physical register) - value of FSR0 offset by value in WREG
n/a
57
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte ---- 0000 32, 57
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 32, 57
WREG
Working Register
xxxx xxxx 32
INDF1
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
n/a
57
POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented
(not a physical register)
n/a
57
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented
(not a physical register)
n/a
57
PREINC1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented
(not a physical register)
n/a
57
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented
(not a physical register) - value of FSR1 offset by value in WREG
n/a
57
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- 0000 33, 57
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 33, 57
BSR
—
—
—
—
Bank Select Register
---- 0000 33, 56
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
n/a
57
POSTINC2
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented
(not a physical register)
n/a
57
POSTDEC2
Uses contents of FSR2 to address data memory - value of FSR2 post-decremented
(not a physical register)
n/a
57
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator
modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
DS39609A-page 52
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