PIC18FXX20 Datasheet, PDF (354/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
Timer1 ...................................................................... 136
Timer1 (16-bit R/W Mode) ........................................ 136
Timer2 ...................................................................... 142
Timer3 ...................................................................... 144
Timer3 in 16-bit R/W Mode ...................................... 144
Timer4 ...................................................................... 148
USART Receive ....................................................... 206
USART Transmit ...................................................... 204
Voltage Reference Output Buffer Example .............. 231
Watchdog Timer ....................................................... 251
BN .................................................................................... 268
BNC .................................................................................. 269
BNN .................................................................................. 269
BNOV ............................................................................... 270
BNZ .................................................................................. 270
BOR. See Brown-out Reset
BOV .................................................................................. 273
BRA .................................................................................. 271
BRG. See Baud Rate Generator
Brown-out Reset (BOR) ............................................. 30, 239
BSF .................................................................................. 271
BTFSC ............................................................................. 272
BTFSS .............................................................................. 272
BTG .................................................................................. 273
BZ ..................................................................................... 274
C
CALL ................................................................................ 274
Capture (CCP Module) ..................................................... 151
Associated Registers ............................................... 153
CCP Pin Configuration ............................................. 151
CCPR1H:CCPR1L Registers ................................... 151
Software Interrupt ..................................................... 151
Timer1/Timer3 Mode Selection ................................ 151
Capture/Compare/PWM (CCP) ........................................ 149
Capture Mode. See Capture
CCP Mode and Timer Resources ............................ 150
CCPRxH Register .................................................... 150
CCPRxL Register ..................................................... 150
Compare Mode. See Compare
Interconnect Configurations ..................................... 150
Module Configuration ............................................... 150
PWM Mode. See PWM
Capture/Compare/PWM Requirements ........................... 328
CLKO and I/O Timing Requirements ....................... 323, 324
Clocking Scheme/Instruction Cycle .................................... 44
CLRF ................................................................................ 275
CLRWDT .......................................................................... 275
Code Examples
16 x 16 Signed Multiply Routine ................................. 86
16 x 16 Unsigned Multiply Routine ............................. 86
8 x 8 Signed Multiply Routine ..................................... 85
8 x 8 Unsigned Multiply Routine ................................. 85
Changing Between Capture Prescalers ................... 151
Data EEPROM Read ................................................. 81
Data EEPROM Refresh Routine ................................ 82
Data EEPROM Write .................................................. 81
Erasing a FLASH Program Memory Row .................. 66
Fast Register Stack .................................................... 44
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................ 57
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service .................................. 139
Initializing PORTA .................................................... 103
Initializing PORTB .................................................... 106
Initializing PORTC ................................................... 109
Initializing PORTD ................................................... 111
Initializing PORTE .................................................... 114
Initializing PORTF .................................................... 117
Initializing PORTG ................................................... 120
Initializing PORTH ................................................... 122
Initializing PORTJ .................................................... 125
Loading the SSPBUF (SSPSR) Register ................. 160
Reading a FLASH Program Memory Word ............... 65
Saving STATUS, WREG and BSR Registers
in RAM ............................................................. 102
Writing to FLASH Program Memory .....................69–70
Code Protection ............................................................... 239
COMF .............................................................................. 276
Comparator
Analog Input Connection Considerations ................ 227
Associated Registers ............................................... 228
Configuration ........................................................... 224
Effects of RESET ..................................................... 227
Interrupts .................................................................. 226
Operation ................................................................. 225
Operation During SLEEP ......................................... 227
Outputs .................................................................... 225
Reference ................................................................ 225
External Signal ................................................ 225
Internal Signal .................................................. 225
Response Time ........................................................ 225
Comparator Module ......................................................... 223
Comparator Specifications ............................................... 317
Comparator Voltage Reference ....................................... 229
Accuracy and Error .................................................. 230
Associated Registers ............................................... 231
Configuring .............................................................. 229
Connection Considerations ...................................... 230
Effects of a RESET .................................................. 230
Operation During SLEEP ......................................... 230
Compare (CCP Module) .................................................. 152
Associated Registers ............................................... 153
CCP Pin Configuration ............................................. 152
CCPR1 Register ...................................................... 152
Software Interrupt .................................................... 152
Special Event Trigger ...............................138, 145, 152
Timer1/Timer3 Mode Selection ................................ 152
Compare (CCP2 Module)
Special Event Trigger .............................................. 220
Configuration Bits ............................................................ 239
Context Saving During Interrupts ..................................... 102
Control Registers
EECON1 and EECON2 ............................................. 62
TABLAT (Table Latch) Register ................................. 64
TBLPTR (Table Pointer) Register .............................. 64
Conversion Considerations .............................................. 348
CPFSEQ .......................................................................... 276
CPFSGT .......................................................................... 277
CPFSLT ........................................................................... 277
DS39609A-page 352
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