PIC18FXX20 Datasheet, PDF (332/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
FIGURE 26-16: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
70
71
72
80
MSb
78
79
79
78
bit6 - - - - - -1
LSb
75, 76
SDI
MSb In
bit6 - - - -1
Note:
74
73
Refer to Figure 26-6 for load conditions.
LSb In
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ input
TssL2scL
TCY
— ns
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 — ns
40
— ns
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 — ns
40
— ns
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
— ns
73A TB2B
Last clock edge of Byte1 to the 1st clock edge of
Byte2
1.5 TCY + 40
—
ns
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
— ns
75
TdoR
SDO data output rise time
PIC18FXX20
—
25 ns
PIC18LFXX20
—
45 ns
76
TdoF
SDO data output fall time
—
25 ns
78
TscR
SCK output rise time
(Master mode)
PIC18FXX20
PIC18LFXX20
—
25 ns
—
45 ns
79
TscF
SCK output fall time (Master mode)
—
25 ns
80
TscH2doV, SDO data output valid after PIC18FXX20
TscL2doV SCK edge
PIC18LFXX20
—
50 ns
—
100 ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
(Note 1)
(Note 1)
(Note 2)
DS39609A-page 330
Advance Information
 2003 Microchip Technology Inc.