PIC18FXX20 Datasheet, PDF (257/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
23.4.1
PROGRAM MEMORY
CODE PROTECTION
The user memory may be read to, or written from, any
location using the Table Read and Table Write instruc-
tions. The device ID may be read with Table Reads.
The configuration registers may be read and written
with the Table Read and Table Write instructions.
In User mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from Table Writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
Table Reads. For a block of user memory with the
EBTRn bit set to ‘0’, a Table Read instruction that exe-
cutes from within that block is allowed to read. A Table
Read instruction that executes from a location outside
of that block is not allowed to read, and will result in
reading ‘0’s. Figures 23-5 through 23-7 illustrate Table
Write and Table Read protection, using devices with a
16-Kbyte block size as the models. The principles illus-
trated are identical for devices with an 8-Kbyte block
size.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
FIGURE 23-5:
TABLE WRITE (WRTn) DISALLOWED
Register Values
TBLPTR = 000FFFh
Program Memory
000000h
0001FFh
000200h
PC = 003FFEh
TBLWT *
003FFFh
004000h
PC = 008FFEh
TBLWT *
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
Configuration Bit Settings
WRTB,EBTRB = 11
WRT0,EBTR0 = 01
WRT1,EBTR1 = 11
WRT2,EBTR2 = 11
WRT3,EBTR3 = 11
Results: All Table Writes disabled to Block n whenever WRTn = 0.
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 255