PIC18FXX20 Datasheet, PDF (72/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BSF
EECON1,EEPGD
BCF
EECON1,CFGS
BSF
EECON1,WREN
BCF
INTCON,GIE
MOVLW 55h
Required MOVWF EECON2
Sequence MOVLW AAh
MOVWF EECON2
BSF
EECON1,WR
NOP
BSF
INTCON,GIE
DECFSZ COUNTER_HI
BRA PROGRAM_LOOP
BCF
EECON1,WREN
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; disable interrupts
; write 55H
; write AAH
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
5.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected RESET, the memory
location just programmed should be verified and repro-
grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset, or a WDT
Time-out Reset during normal operation. In these situ-
ations, users can check the WRERR bit and rewrite the
location.
5.5.4
PROTECTION AGAINST SPURIOUS
WRITES
To protect against spurious writes to FLASH program
memory, the write initiate sequence must also be fol-
lowed. See “Special Features of the CPU”
(Section 23.0) for more detail.
5.6 FLASH Program Operation During
Code Protection
See “Special Features of the CPU” (Section 23.0) for
details on code protection of FLASH program memory.
TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit21
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
TABLAT Program Memory Table Latch
INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF
EECON2 EEPROM Control Register2 (not a physical register)
EECON1 EEPGD CFGS
—
FREE WRERR WREN
WR
IPR2
—
CMIP
—
EEIP BCLIP LVDIP TMR3IP
PIR2
—
CMIF
—
EEIF BCLIF LVDIF TMR3IF
PIE2
—
CMIE
—
EEIE BCLIE LVDIE TMR3IE
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'.
Shaded cells are not used during FLASH/EEPROM access.
RBIF
RD
CCP2IP
CCP2IF
CCP2IE
Value on:
POR,
BOR
Value on
all other
RESETS
--00 0000 --00 0000
0000 0000
0000 0000
0000 0000
0000 0000
—
0000 0000
0000 0000
0000 0000
0000 0000
—
xx-0 x000 uu-0 u000
---1 1111 ---1 1111
---0 0000 ---0 0000
---0 0000 ---0 0000
DS39609A-page 70
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 2003 Microchip Technology Inc.