PIC18FXX20 Datasheet, PDF (171/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I²C MODE)
R/W-0
GCEN
bit 7
R/W-0
ACKSTAT
R/W-0
ACKDT
R/W-0
ACKEN
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
bit 0
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence IDLE
bit 3
RCEN: Receive Enable bit (Master Mode only)
1 = Enables Receive mode for I²C
0 = Receive IDLE
bit 2
PEN: STOP Condition Enable bit (Master mode only)
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition IDLE
bit 1
RSEN: Repeated START Condition Enabled bit (Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins.
Automatically cleared by hardware.
0 = Repeated START condition IDLE
bit 0
SEN: START Condition Enabled/Stretch Enabled bit
In Master mode:
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition IDLE
In Slave mode:
1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)
0 = Clock stretching is disabled
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 169