PIC18FXX20 Datasheet, PDF (206/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
18.2 USART Asynchronous Mode
In this mode, the USARTs use standard
non-return-to-zero (NRZ) format (one START bit, eight
or nine data bits and one STOP bit). The most common
data format is 8 bits. An on-chip dedicated 8-bit baud
rate generator can be used to derive standard baud
rate frequencies from the oscillator. The USART trans-
mits and receives the LSbit first. The USART’s trans-
mitter and receiver are functionally independent, but
use the same data format and baud rate. The baud rate
generator produces a clock, either 16 or 64 times the
bit shift rate, depending on bit BRGH (TXSTAx<2>).
Parity is not supported by the hardware, but can be
implemented in software (and stored as the ninth data
bit). Asynchronous mode is stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTAx<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
18.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer, TXREGx.
The TXREGx register is loaded with data in software.
The TSR register is not loaded until the STOP bit has
been transmitted from the previous load. As soon as
the STOP bit is transmitted, the TSR is loaded with new
data from the TXREGx register (if available). Once the
TXREGx register transfers the data to the TSR register
(occurs in one TCY), the TXREGx register is empty and
flag bit, TXx1IF (PIR1<4> for USART1, PIR3<4> for
USART2), is set. This interrupt can be enabled/dis-
abled by setting/clearing enable bit, TXxIE (PIE1<4>
for USART1, PIE<4> for USART2). Flag bit TXxIF will
be set, regardless of the state of enable bit TXxIE and
cannot be cleared in software. It will reset only when
new data is loaded into the TXREGx register. While flag
bit TXIF indicated the status of the TXREGx register,
another bit, TRMT (TXSTAx<1>), shows the status of
the TSR register. Status bit TRMT is a read only bit,
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
To set up an asynchronous transmission:
1. Initialize the SPBRGx register for the appropri-
ate baud rate. If a high speed baud rate is
desired, set bit BRGH (Section 18.1).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXxIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREGx register (starts
transmission).
Note:
TXIF is not cleared immediately upon load-
ing data into the transmit buffer TXREG.
The flag bit becomes valid in the second
instruction cycle following the load
instruction.
FIGURE 18-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
TXIF
Interrupt
MSb
(8)
TXREG Register
8
LSb
•••
0
TSR Register
Pin Buffer
and Control
TX pin
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator
TX9
TX9D
TRMT
SPEN
DS39609A-page 204
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 2003 Microchip Technology Inc.