PIC18FXX20 Datasheet, PDF (327/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
FIGURE 26-10: PROGRAM MEMORY WRITE TIMING DIAGRAM
OSC1
A<19:16>
BA0
AD<15:0>
ALE
CE
WRH or
WRL
UB or
LB
Q1
Q2
Address
150
151
171
171A
157
Q3
Q4
Address
166
Data
153
156
154
Q1
Q2
Address
Address
157A
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < 125°C unless otherwise stated.
TABLE 26-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ Max
150 TadV2alL Address out valid to ALE ↓ (address setup time)
0.25 TCY – 10 —
—
151 TalL2adl ALE ↓ to address out invalid (address hold time)
5
—
—
153 TwrH2adl WRn ↑ to data out invalid (data hold time)
5
—
—
154 TwrL
WRn pulse width
0.5 TCY – 5 0.5 TCY —
156 TadV2wrH Data valid before WRn ↑ (data setup time)
0.5 TCY – 10 —
—
157 TbsV2wrL Byte select valid before WRn ↓ (byte select setup time) 0.25 TCY
—
—
157A TwrH2bsI WRn ↑ to byte select invalid (byte select hold time) 0.125 TCY – 5 —
—
166 TalH2alH ALE ↑ to ALE ↑ (cycle time)
—
0.25 TCY —
171
TalH2csL Chip Enable active to ALE ↓
0.25 TCY – 20 —
—
171A TubL2oeH AD valid to Chip Enable active
—
—
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 325