PIC18FXX20 Datasheet, PDF (331/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
FIGURE 26-15:
RE2/CS
PARALLEL SLAVE PORT TIMING (PIC18F8X20)
RE0/RD
RE1/WR
65
RD7:RD0
64
Note: Refer to Figure 26-6 for load conditions.
62
63
TABLE 26-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8X20)
Param.
No.
Symbol
Characteristic
Min Max Units
Conditions
62
TdtV2wrH Data in valid before WR ↑ or CS ↑
(setup time)
20 — ns
25 — ns Extended Temp. range
63
TwrH2dtI WR ↑ or CS ↑ to data–in
PIC18FXX20 20 — ns
invalid (hold time)
PIC18LFXX20 35 — ns
64
TrdL2dtV RD ↓ and CS ↓ to data–out valid
— 80 ns
— 90 ns Extended Temp. range
65
TrdH2dtI RD ↑ or CS ↓ to data–out invalid
10 30 ns
66
TibfINH Inhibit of the IBF flag bit being cleared from
— 3 TCY
WR ↑ or CS ↑
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 329