PIC18F2331_10 Datasheet, PDF(73/392 Page) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

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PIC18F2331_10 Datasheet, PDF (73/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

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PIC18F2331/2431/4331/4431

TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

PDC0L

PWM Duty Cycle #0L Register (lower 8 bits)

0000 0000

PDC0H

UNUSED

PWM Duty Cycle #0H Register (upper 6 bits)

--00 0000

PDC1L

PWM Duty Cycle #1L Register (lower 8 bits)

0000 0000

PDC1H

UNUSED

PWM Duty Cycle #1H Register (upper 6 bits)

--00 0000

PDC2L

PWM Duty Cycle #2L Register (lower 8 bits)

0000 0000

PDC2H

UNUSED

PWM Duty Cycle #2H Register (upper 6 bits)

--00 0000

PDC3L(4)

PWM Duty Cycle #3L Register (lower 8 bits)

0000 0000

PDC3H(4)

UNUSED

PWM Duty Cycle #3H Register (upper 6 bits)

--00 0000

SEVTCMPL PWM Special Event Compare Register (lower 8 bits)

0000 0000

SEVTCMPH

UNUSED

PWM Special Event Compare Register (upper 4 bits)

---- 0000

PWMCON0

â

PWMEN2 PWMEN1 PWMEN0

PMOD3

PMOD2

PMOD1

PMOD0 -111 0000

PWMCON1

SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR

â

UDIS

OSYNC 0000 0-00

DTCON

DTPS1

DTPS0

DT5

DT4

DT3

DT2

DT1

DT0

0000 0000

FLTCONFIG

BRFEN

FLTBS(4) FLTBMOD(4) FLTBEN(4) FLTCON

FLTAS

FLTAMOD FLTAEN 0000 0000

OVDCOND

POVD7(4)

POVD6(4)

POVD5

POVD4

POVD3

POVD2

POVD1

POVD0 1111 1111

OVDCONS

POUT7(4)

POUT6(4)

POUT5

POUT4

POUT3

POUT2

POUT1

POUT0 0000 0000

CAP1BUFH/ Capture 1 Register High Byte/Velocity Register High Byte

VELRH

xxxx xxxx

CAP1BUFL/

VELRL

Capture 1 Register Low Byte/Velocity Register Low Byte

xxxx xxxx

CAP2BUFH/ Capture 2 Register High Byte/QEI Position Counter Register High Byte

POSCNTH

xxxx xxxx

CAP2BUFL/

POSCNTL

Capture 2 Register Low Byte/QEI Position Counter Register Low Byte

xxxx xxxx

CAP3BUFH/ Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte

MAXCNTH

xxxx xxxx

CAP3BUFL/

MAXCNTL

Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte

xxxx xxxx

CAP1CON

â

CAP1REN

â

â

CAP1M3

CAP1M2

CAP1M1

CAP1M0 -0-- 0000

CAP2CON

â

CAP2REN

â

â

CAP2M3

CAP2M2

CAP2M1

CAP2M0 -0-- 0000

CAP3CON

â

CAP3REN

â

â

CAP3M3

CAP3M2

CAP3M1

CAP3M0 -0-- 0000

DFLTCON

â

FLT4EN

FLT3EN

FLT2EN

FLT1EN

FLTCK2

FLTCK1

FLTCK0 -000 0000

Legend:

Note 1:

2:

3:

4:

5:

x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.

RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read

â0â in all other oscillator modes.

RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read â0â in all other modes.

Bit 21 of the PC is only available in Test mode and Serial Programming modes.

These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as â0â.

The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to â0â; otherwise, RE3

reads â0â. This bit is read-only.

ï£ 2010 Microchip Technology Inc.

DS39616D-page 73

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