PIC18F2331_10 Datasheet, PDF (53/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 5-7:
TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
TPWRT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL  2 ms max. First three stages of the PWRT timer.
TABLE 5-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program RCON
Counter Register
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
0000h 0--1 1100 1 1 1 0
0
0
0
RESET Instruction
0000h 0--0 uuuu 0 u u u
u
u
u
Brown-out
0000h 0--1 11u- 1 1 1 u
0
u
u
MCLR Reset during power-managed
0000h 0--u 1uuu u 1 u u
u
u
u
Run modes
MCLR Reset during power-managed Idle 0000h 0--u 10uu u 1 0 u
u
u
u
and Sleep modes
WDT Time-out during full power or
power-managed Run modes
0000h 0--u 0uuu u 0 u u
u
u
u
MCLR Reset during full-power execution
u
u
Stack Full Reset (STVREN = 1)
0000h 0--u uuuu u u u u
u
1
u
Stack Underflow Reset (STVREN = 1)
u
1
Stack Underflow Error (not an actual
0000h u--u uuuu u u u u
u
u
1
Reset, STVREN = 0)
WDT time-out during power-managed Idle PC + 2 u--u 00uu u 0 0 u
u
u
u
or Sleep modes
Interrupt exit from power-managed modes PC + 2⁽¹⁾ u--u u0uu u u 0
u
u
u
u
Legend:
Note 1:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
 2010 Microchip Technology Inc.
DS39616D-page 53