PIC18F2331_10 Datasheet, PDF (237/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
20.5 EUSART Synchronous Slave
Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the RC6/TX/CK/SS pin (instead
of being supplied internally in Master mode). This
allows the device to transfer or receive data while in
any low-power mode.
20.5.1
EUSART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit, TXIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit, TXIF, will now be set.
e) If enable bit, TXIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TXIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
54
PIR1
—
ADIF
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
57
PIE1
—
ADIE
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
57
IPR1
—
ADIP
RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
57
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
56
TXREG
EUSART Transmit Register
56
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
56
BAUDCON
—
RCIDL
—
SCKP BRG16
—
WUE ABDEN
56
SPBRGH EUSART Baud Rate Generator Register High Byte
56
SPBRG
EUSART Baud Rate Generator Register Low Byte
56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
 2010 Microchip Technology Inc.
DS39616D-page 237