PIC18F2331_10 Datasheet, PDF(215/392 Page) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIC18F2331_10 Datasheet, PDF (215/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

◁

PIC18F2331/2431/4331/4431

19.3.1.3 Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin, SCK/SCL, is held low.

The transmit data must be loaded into the SSPBUF

register, which also loads the SSPSR register. Then,

pin, SCK/SCL, should be enabled by setting bit, CKP

(SSPCON<4>). The master must monitor the SCL pin

prior to asserting another clock pulse. The slave

devices may be holding off the master by stretching the

clock. The eight data bits are shifted out on the falling

edge of the SCL input. This ensures that the SDA signal

is valid during the SCL high time (Figure 19-7).

An SSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF, must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. Flag bit, SSPIF, is set on the falling edge of

the ninth clock pulse.

As a slave-transmitter, the ACK pulse from the master-

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then the

data transfer is complete. When the ACK is latched by

the slave, the slave logic is reset and the slave then

monitors for another occurrence of the Start bit. If the

SDA line was low (ACK), the transmit data must be

loaded into the SSPBUF register, which also loads the

SSPSR register. Then pin, SCK/SCL, should be enabled

by setting bit CKP.

FIGURE 19-7:

I2Câ¢ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

Receiving Address

R/W = 1

A7 A6 A5 A4 A3 A2 A1

ACK

Transmitting Data ACK

D7 D6 D5 D4 D3 D2 D1 D0

SCL S

1 23456 789

12345 6 789

Data in

SCL held low

P

sampled

while CPU

responds to SSPIF

SSPIF (PIR1<3>)

Cleared in software

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

SSPBUF is written in software

From SSP Interrupt

Service Routine

Set bit after writing to SSPBUF

(SSPBUF must be written to

before the CKP bit can be set)

ï£ 2010 Microchip Technology Inc.

DS39616D-page 215

▷