PIC18F2331_10 Datasheet, PDF (39/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
4.0 POWER-MANAGED MODES
PIC18F2331/2431/4331/4431 devices offer a total of
seven operating modes for more efficient power
management. These modes provide a variety of
options for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).
There are three categories of power-managed modes:
• Run modes
• Idle modes
• Sleep mode
These categories define which portions of the device
are clocked, and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power-managed modes include several power-
saving features offered on previous PIC^® devices. One
is the clock switching feature, offered in other PIC18
devices, allowing the controller to use the Timer1 oscil-
lator in place of the primary oscillator. Also included is
the Sleep mode, offered by all PIC devices, where all
device clocks are stopped.
4.1 Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and the
selection of a clock source. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS<1:0> bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 4-1.
4.1.1 CLOCK SOURCES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the FOSC<3:0>
Configuration bits
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block (for RC modes)
4.1.2
ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 4.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
TABLE 4-1: POWER-MANAGED MODES
Mode
OSCCON Bits<7,1:0>
IDLEN⁽¹⁾ SCS<1:0>
Module Clocking
CPU Peripherals
Available Clock and Oscillator Source
Sleep
0
N/A
Off
Off
None – All clocks are disabled
PRI_RUN
N/A
00
Clocked
Clocked Primary – LP, XT, HS, HSPLL, RC, EC and
Internal Oscillator Block.⁽²⁾
This is the normal, full-power execution mode.
SEC_RUN
N/A
01
Clocked
Clocked Secondary – Timer1 Oscillator
RC_RUN
N/A
1x
Clocked
Clocked Internal Oscillator Block⁽²⁾
PRI_IDLE
1
00
Off
Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE
1
01
Off
Clocked Secondary – Timer1 Oscillator
RC_IDLE
1
1x
Off
Clocked Internal Oscillator Block⁽²⁾
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
 2010 Microchip Technology Inc.
DS39616D-page 39