PIC18F2331_10 Datasheet, PDF (168/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 17-13:
QEA
QEB
vel_out
velcap
TMR5⁽²⁾
VELOCITY MEASUREMENT TIMING⁽¹⁾
Forward
Reverse
VELR⁽²⁾
cnt_reset⁽³⁾
Old Value
1529
1537
IC1IF⁽⁴⁾
CAP1REN
Q1
Q1
Q1
Instr.
Execution ^{BCF T5CON, VELM BCF PIE2, IC1IE BSF PIE2, IC1IE}
MOVWF QEICON⁽⁵⁾
Note 1:
2:
3:
4:
5:
Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio
is set to divide-by-4 (PDEC<1:0> = 01).
The VELR register latches the TMR5 count on the “velcap” capture pulse. Timer5 must be set to the Synchronous Timer
or Counter mode. In this example, it is set to the Synchronous Timer mode, where the TMR5 prescaler divide ratio = 1
(i.e., Timer5 Clock = TCY).
The TMR5 counter is reset on the next Q1 clock cycle following the “velcap” pulse. The TMR5 value is unaffected
when the Velocity Measurement mode is first enabled (VELM = 0). The velocity postscaler values must be
reconfigured to their previous settings when re-entering Velocity Measurement mode. While making speed
measurements of very slow rotational speeds (e.g., servo-controller applications), the Velocity Measurement mode
may not provide sufficient precision. The Pulse-Width Measurement mode may have to be used to provide the
additional precision. In this case, the input pulse is measured on the CAP1 input pin.
IC1IF interrupt is enabled by setting IC1IE as follows: BSF PIE2, IC1IE. Assume IC1E bit is placed in the PIE2
(Peripheral Interrupt Enable 2) register in the target device. The actual IC1IF bit is written on the Q2 rising edge.
The post decimation value is changed from PDEC = 01 (decimate by 4) to PDEC = 00 (decimate by 1).
17.2.6.2 Velocity Postscaler
The velocity event pulse (velcap, see Figure 17-12)
serves as the TMR5 capture trigger to IC1 while in the
Velocity mode. The number of velocity events are
reduced by the velocity postscaler before they are used
as the input capture clock. The velocity event reduction
ratio can be set with the PDEC<1:0> control bits
(QEICON<1:0>) to 1:4, 1:16, 1:64 or no reduction (1:1).
The velocity postscaler settings are automatically
reloaded from their previous values as the Velocity
mode is re-enabled.
17.2.6.3 CAP1REN in Velocity Mode
The TMR5 value can be reset (TMR5 register
pair = 0000h) on a velocity event capture by setting
the CAP1REN bit (CAP1CON<6>). When CAP1REN
is cleared, the TMR5 time base will not be reset on
any velocity event capture pulse. The VELR register
pair, however, will continue to be updated with the
current TMR5 value.
DS39616D-page 168
 2010 Microchip Technology Inc.