PIC18F2331_10 Datasheet, PDF (214/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
19.3.1.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to the user’s firmware.
An SSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
FIGURE 19-6:
I²C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
A7
Receiving Address
A6 A5 A4 A3 A2
R/W = 0
A1
ACK _D7
Receiving Data
D6 D5 D4 D3 D2
D1
ACK
D0
D7
D6
Receiving Data
D5 D4 D3 D2
D1
ACK
D0
SCL S
1 2 3 4 5 6 789 1 2 3 4 5 678 9 1 234 56 7 89
P
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Cleared in software
SSPBUF register is read
SSPOV bit is set because the SSPBUF register is still full
ACK is not sent
Bus master
terminates
transfer
DS39616D-page 214
 2010 Microchip Technology Inc.