PIC18F2331_10 Datasheet, PDF (50/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
5.5 Device Reset Timers
PIC18F2331/2431/4331/4431 devices incorporate
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
5.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of PIC18F2331/2431/
4331/4431 devices is an 11-bit counter that uses the
INTRC source as the clock input. This yields an
approximate time interval of 2,048 x 32 s = 65.6 ms.
While the PWRT is counting, the device is held in
Reset. The power-up time delay depends on the
INTRC clock and will vary from chip to chip due to tem-
perature and process variation. See DC Parameter 33
for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
5.5.2
OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a
1,024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (Parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes, and on Power-on Reset or on exit from
most power-managed modes.
5.5.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
Lock Time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
5.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, the PWRT time-out
is invoked (if enabled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 5-3 through
Figure 5-7 depict time-out sequences on power-up,
with the Power-up Timer enabled and the device oper-
ating in HS Oscillator mode. Figure 5-3 through
Figure 5-6 also apply to devices operating in XT or LP
modes.
For devices in RC mode, and with the PWRT disabled,
there will be no time-out at all. Since the time-outs
occur from the POR pulse, if MCLR is kept low long
enough, all time-outs will expire. Bringing MCLR high
will begin execution immediately (Figure 5-5). This is
useful for testing purposes or synchronization of more
than one PIC18FXXXX device operating in parallel.
TABLE 5-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up⁽²⁾ and Brown-out
PWRTEN = 0
PWRTEN = 1
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
66 ms⁽¹⁾ + 1024 TOSC + 2 ms⁽²⁾
66 ms⁽¹⁾ + 1024 TOSC
66 ms⁽¹⁾
66 ms⁽¹⁾
66 ms⁽¹⁾
1024 TOSC + 2 ms⁽²⁾
1024 TOSC
—
—
—
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the 4x PLL to lock.
Exit From
Power-Managed Mode
1024 TOSC + 2 ms⁽²⁾
1024 TOSC
—
—
—
DS39616D-page 50
 2010 Microchip Technology Inc.