PIC18F2331_10 Datasheet, PDF (63/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or a POR occurs.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset as the contents
of the SFRs are not affected.
FIGURE 6-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
TOSU
00h
TOSH
1Ah
Return Address Stack
TOSL
34h
11111
11110
11101
STKPTR<4:0>
00010
Top-of-Stack
00011
001A34h 00010
000D58h 00001
00000
REGISTER 6-1: STKPTR: STACK POINTER REGISTER
R/C-0
R/C-0
U-0
STKFUL⁽¹⁾ STKUNF⁽¹⁾
—
bit 7
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4-0
STKFUL: Stack Full Flag bit⁽¹⁾
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit⁽¹⁾
1 = Stack underflow occurred
0 = Stack underflow did not occur
Unimplemented: Read as ‘0’
SP<4:0>: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
 2010 Microchip Technology Inc.
DS39616D-page 63