PIC18F2331_10 Datasheet, PDF (238/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
20.5.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this Low-Power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register. If the RCIE enable bit is set, the inter-
rupt generated will wake the chip from Low-Power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RCIE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
5. Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
6. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
54
PIR1
—
ADIF
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
57
PIE1
—
ADIE
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
57
IPR1
—
ADIP
RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
57
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
56
RCREG
EUSART Receive Register
56
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
56
BAUDCON
—
RCIDL
—
SCKP BRG16 —
WUE ABDEN
56
SPBRGH EUSART Baud Rate Generator Register High Byte
56
SPBRG
EUSART Baud Rate Generator Register Low Byte
56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS39616D-page 238
 2010 Microchip Technology Inc.