PIC18F2331_10 Datasheet, PDF (213/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
19.3.1.1 Addressing
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The Buffer Full bit, BF, is set.
c) An ACK pulse is generated.
d) SSP Interrupt Flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave (Figure 19-7). The five Most
Significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the
second address byte. For a 10-bit address, the first
byte would equal ‘1111 0 A9 A8 0’, where A9 and
A8 are the two MSbs of the address.
The sequence of events for 10-Bit Addressing mode is
as follows, with Steps 7-9 for slave-transmitter:
1. Receive first (high) byte of address (SSPIF, BF
and UA bits are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit, UA, and releases the
SCL line).
3. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
4. Receive second (low) byte of address (SSPIF,
BF and UA bits are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit, UA.
6. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (SSPIF and
BF bits are set).
9. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
TABLE 19-2: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
BF
SSPOV
SSPSR  SSPBUF
Generate ACK
Pulse
Set SSPIF Bit
(SSP interrupt occurs
if enabled)
0
1
1
0
Note:
0
Yes
Yes
Yes
0
No
No
Yes
1
No
No
Yes
1
No
No
Yes
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
 2010 Microchip Technology Inc.
DS39616D-page 213