PIC18F2331_10 Datasheet, PDF (46/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
4.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval,
TCSD, following the wake event, is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 4-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
Before Wake-up
Clock Source
After Wake-up
Exit Delay
Clock Ready Status
Bit (OSCCON)
LP, XT, HS
Primary Device Clock
(PRI_IDLE mode)
HSPLL
EC, RC
TCSD⁽¹⁾
OSTS
INTOSC⁽²⁾
IOFS
LP, XT, HS
TOST⁽³⁾
T1OSC
HSPLL
EC, RC
TOST + t_rc⁽³⁾
TCSD⁽¹⁾
OSTS
INTOSC⁽²⁾
TIOBST⁽⁴⁾
IOFS
LP, XT, HS
TOST⁽³⁾
INTOSC⁽³⁾
HSPLL
EC, RC
TOST + t_rc⁽³⁾
TCSD⁽¹⁾
OSTS
INTOSC⁽²⁾
None
IOFS
LP, XT, HS
TOST⁽³⁾
None
(Sleep mode)
HSPLL
EC, RC
TOST + t_rc⁽³⁾
TCSD⁽¹⁾
OSTS
INTOSC⁽²⁾
TIOBST⁽⁴⁾
IOFS
Note 1: TCSD (Parameter 38) is a required delay when waking from Sleep and all Idle modes, and runs concur-
rently with any other required delays (see Section 4.4 “Idle Modes”).
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer (Parameter 32). t_rc is the PLL Lock-out Timer (Parameter F12); it is
also designated as TPLL.
4: Execution continues during TIOBST (Parameter 39), the INTOSC stabilization period.
DS39616D-page 46
 2010 Microchip Technology Inc.