PIC18F2331_10 Datasheet, PDF (47/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
5.0 RESET
The PIC18F2331/2431/4331/4431 devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and the operation of the various start-
up timers. Stack Reset events are covered in
Section 6.1.2.4 “Stack Full/Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
MCLR
VDD
External Reset
MCLRE
( )_IDLE
Sleep
WDT
Time-out
VDD Rise POR Pulse
Detect
Brown-out
Reset
BOREN
OSC1
OST/PWRT
OST
1024 Cycles
10-Bit Ripple Counter
32 s
INTRC
PWRT 65.5 ms
11-Bit Ripple Counter
S
Chip_Reset
R
Q
Note 1: See Table 5-1 for time-out situations.
Enable PWRT
Enable OST⁽¹⁾
 2010 Microchip Technology Inc.
DS39616D-page 47