PIC18F2331_10 Datasheet, PDF (385/392 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

PIC18F2331/2431/4331/4431
DEVID2 (Device ID 2) ............................................... 273
DFLTCON (Digital Filter Control) .............................. 169
DTCON (Dead-Time Control) ................................... 192
EECON1 (Data EEPROM Control 1) .......................... 87
EECON1 (EEPROM Control 1)................................... 80
FLTCONFIG (Fault Configuration)............................ 201
INTCON (Interrupt Control)......................................... 99
INTCON2 (Interrupt Control 2).................................. 100
INTCON3 (Interrupt Control 3).................................. 101
IPR1 (Peripheral Interrupt Priority 1)......................... 108
IPR2 (Peripheral Interrupt Priority 2)......................... 109
IPR3 (Peripheral Interrupt Priority 3)......................... 110
LVDCON (Low-Voltage Detect Control).................... 257
OSCCON (Oscillator Control) ..................................... 36
OSCTUNE (Oscillator Tuning) .................................... 33
OVDCOND (Output Override Control) ...................... 196
OVDCONS (Output State) ........................................ 196
PIE1 (Peripheral Interrupt Enable 1)......................... 105
PIE2 (Peripheral Interrupt Enable 2)......................... 106
PIE3 (Peripheral Interrupt Enable 3)......................... 107
PIR1 (Peripheral Interrupt Request (Flag) 1) ............ 102
PIR2 (Peripheral Interrupt Request (Flag) 2) ............ 103
PIR3 (Peripheral Interrupt Request (Flag) 3) ............ 104
PTCON0 (PWM Timer Control 0) ............................. 178
PTCON1 (PWM Timer Control 1) ............................. 178
PWMCON0 (PWM Control 0) ................................... 179
PWMCON1 (PWM Control 1) ................................... 180
QEICON (QEI Control).............................................. 162
RCON (Reset Control) ........................................ 48, 111
RCSTA (Receive Status and Control)....................... 219
SSPCON (SSP Control)............................................ 207
SSPSTAT (SSP Status)............................................ 206
STATUS...................................................................... 74
STKPTR (Stack Pointer) ............................................. 63
Summary............................................................... 70–73
TRISE ....................................................................... 124
TXSTA (Transmit Status and Control) ...................... 218
T0CON (Timer0 Control)........................................... 127
T1CON (Timer1 Control)........................................... 131
T2CON (Timer2 Control)........................................... 136
T5CON (Timer5 Control)........................................... 139
WDTCON (Watchdog Timer Control) ....................... 275
RESET .............................................................................. 313
Reset................................................................................... 47
Resets ............................................................................... 263
RETFIE ............................................................................. 314
RETLW ............................................................................. 314
RETURN ........................................................................... 315
Return Address Stack ......................................................... 62
Return Stack Pointer (STKPTR) ......................................... 62
Revision History ................................................................ 375
RLCF................................................................................. 315
RLNCF .............................................................................. 316
RRCF ................................................................................ 316
RRNCF ............................................................................. 317
S
S (Start) Bit ....................................................................... 206
SCK................................................................................... 205
SCL ................................................................................... 212
SDI .................................................................................... 205
SDO .................................................................................. 205
SEC_IDLE Mode................................................................. 44
SEC_RUN Mode ................................................................. 40
Serial Clock (SCK) Pin ...................................................... 205
Serial Data In (SDI) Pin..................................................... 205
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Serial Data Out (SDO) Pin................................................ 205
SETF ................................................................................ 317
Single-Supply ICSP Programming.................................... 282
Slave Select (SS) Pin ....................................................... 205
SLEEP .............................................................................. 318
Sleep
OSC1 and OSC2 Pin States....................................... 37
Software Simulator (MPLAB SIM) .................................... 327
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ............................................ 263
Special Function Registers
Map............................................................................. 69
SPI Mode (SSP) ............................................................... 205
Associated Registers................................................ 211
Serial Clock .............................................................. 205
Serial Data In............................................................ 205
Serial Data Out ......................................................... 205
Slave Select.............................................................. 205
SS ..................................................................................... 205
SSP
Overview.
TMR2 Output for Clock Shift............................. 136, 137
SSPEN Bit ........................................................................ 207
SSPM<3:0> Bits ............................................................... 208
SSPOV Bit ........................................................................ 207
Stack Full/Underflow Resets............................................... 64
Status Bits, Significance and Initialization for
RCON Register........................................................... 53
SUBFWB .......................................................................... 318
SUBLW ............................................................................. 319
SUBWF............................................................................. 319
SUBWFB .......................................................................... 320
SWAPF ............................................................................. 320
Synchronous Serial Port. See SSP.
T
TABLAT Register................................................................ 88
Table Pointer Operations (table)......................................... 88
TBLPTR Register................................................................ 88
TBLRD .............................................................................. 321
TBLWT ............................................................................. 322
Time-out in Various Situations (table)................................. 50
Timer0 .............................................................................. 127
Associated Registers................................................ 129
Clock Source Edge Select (T0SE Bit) ...................... 129
Clock Source Select (T0CS Bit) ............................... 129
Interrupt .................................................................... 129
Operation.................................................................. 129
Prescaler .................................................................. 129
Switching Assignment ...................................... 129
Prescaler. See Prescaler, Timer0.
16-Bit Mode Timer Reads and Writes ...................... 129
Timer1 .............................................................................. 131
Associated Registers................................................ 135
Interrupt .................................................................... 134
Operation.................................................................. 132
Oscillator........................................................... 131, 133
Layout Considerations...................................... 133
Overflow Interrupt ..................................................... 131
Resetting, Using a Special Event Trigger
Output (CCP).................................................... 134
Special Event Trigger (CCP) .................................... 147
TMR1H Register....................................................... 131
TMR1L Register ....................................................... 131
Use as a Real-Time Clock (RTC) ............................. 134
16-Bit Read/Write Mode ........................................... 134
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