1EDI2001AS_15 Datasheet, PDF (98/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Register Description
Secondary Error Register
This register provides information on the error status of the device.
SER
Secondary Error Register
Offset
13_H
Wakeup Value
n.a.
Reset Value
8011_H
15
RST2
rhs
7
OVLO3ER
rhs
14
OCPER
rhs
6
OTER
rhs
13
12
11
10
DESATER UVLO2ER OVLO2ER UVLO3ER
rhs
rhs
rhs
rhs
5
4
3
2
OSTER
CER2
0
rhs
rhs
r
9
VMTO
rhs
1
LMI
rh
8
GER
rhs
0
P
rh
Field
RST2
OCPER
DESATER
UVLO2ER
Bits
Type Description
15
rhs
Hard Reset Secondary Flag
This bit indicates if a hard reset event has been detected
on the secondary chip (due to a V_CC2 power-up).
0_B: No hard reset event has been detected.
1_B: A hard reset event has been detected.
This bit is sticky.
14
rhs
OCP Error Flag
This bit indicates if an OCP event has been detected.
0_B: No event has been detected.
1_B: An event has been detected.
This bit is sticky.
Note: This bit can not be cleared while an error condition
is active (bit SSTAT2.OCPC1 set).
13
rhs
DESAT Error Flag
This bit indicates if a DESAT event has been detected.
0_B: No event has been detected.
1_B: An event has been detected.
This bit is sticky.
12
rhs
UVLO2 Error Flag
This bit indicates if an Undervoltage Lockout event (on
V_CC2) has been detected.
0_B: No event has been detected.
1_B: An event has been detected.
This bit is sticky.
Note: This bit can not be cleared while an error condition
is active (bit SSTAT2.UVLO2M set).
Datasheet
98
Hardware Description
Rev. 3.1, 2015-07-30