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| 1EDI2001AS_15 Datasheet, PDF (84/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step | |||
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EiceDRIVER⢠SIL
1EDI2001AS
Register Description
Primary Configuration Register
This register is used to select the configuration of the device.
PCFG
Primary Configuration Register
Offset
04H
Wakeup Value
n.a.
Reset Value
0004H
15
8
0
r
7
6
5
4
3
2
1
0
0
OSMAEN OSTAEN
Res
PAREN
LMI
P
r
rw
rw
rw
rw
rh
rh
Field
0
OSMAEN
OSTAEN
Res
PAREN
LMI
P
Bits
Type Description
15:6
r
Reserved
Read as 0B.
5
rw
NFLTA Activation on OSM Event Enable Bit
This bit enables the activation of signal NFLTA in case of
a transition from 0B to 1B of bit PSTAT2.OSTC.
0B: NFLTA activation is disabled.
1B: NFLTA activation is enabled
4
rw
NFLTA Activation on Tristate Event Enable Bit
This bit enables the activation of signal NFLTA in case of
a transition from 0B to 1B of bit PER.OSTER.
0B: NFLTA activation is disabled.
1B: NFLTA activation is enabled
3
rw
Reserved
This bit is reserved. It should be written with 0H.
2
rw
Parity Enable Bit
This bit indicates if the SPI parity error detection is active
(reception only).
0B: Parity Check is disabled.
1B: Parity Check is enabled.
1
rh
Last Message Invalid Notification
This bit indicates if the last received SPI Message was
correctly processed by the device.
0B: Previous Message was processed correctly.
1B: Previous Message was discarded.
0
rh
Parity Bit
Odd Parity Bit.
Datasheet
84
Hardware Description
Rev. 3.1, 2015-07-30
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