1EDI2001AS_15 Datasheet, PDF (85/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Register Description
Primary Control Register
This register is used to control the device during run-time.
PCTRL
Primary Control Register
Offset
06_H
Wakeup Value
n.a.
Reset Value
0001_H
15
0
r
7
6
5
4
3
2
0
CLRS
CLRP
GTCT
GPON
r
rwh
rwh
rwh
rw
8
1
0
LMI
P
rh
rh
Field
0
CLRS
CLRP
GTCT
GPON
Bits
Type Description
15:7
r
Reserved
Read as 0_B.
6
rwh
Clear Secondary Request Bit
This bit is used to clear the sticky bits on the secondary
side.
0_B: No action.
1_B: Clear sticky bits.
This bit is automatically cleared by hardware.
5
rwh
Clear Primary Request Bit
This bit is used to clear the sticky bits on the primary side.
0_B: No action.
1_B: Clear sticky bits and deassert signals NFLTA and
NFLTB.
This bit is automatically cleared by hardware.
4
rwh
Gate Timing Capture Trigger Bit
This bit is used to trigger the timing capture mechanism
measurements of the Gate Monitoring function.
0_B: No action.
1_B: Timing capture triggered.
This bit is automatically cleared by hardware
3:2
rw
Gate Turn-On Plateau Level Configuration
This bit field is used to configure the voltage of the
plateau during Weak Turn-On.
0_H: V_GPON0 selected.
1_H: V_GPON1 selected.
2_H: V_GPON2 selected.
3_H: Reserved (WTO) .
Datasheet
85
Hardware Description
Rev. 3.1, 2015-07-30