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| 1EDI2001AS_15 Datasheet, PDF (113/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step | |||
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Secondary Clock Supervision Register
This register is for internal purpose only.
SCS
Secondary Clock Supervision Register
15
7
0
r
EiceDRIVER⢠SIL
1EDI2001AS
Register Description
Offset
1FH
CS2
rh
Wakeup Value
n.a.
Reset Value
0001H
8
2
1
0
LMI
P
rh
rh
Field
CS2
0
LMI
P
Bits
Type Description
15:8
rh
Secondary Clock Supervision
This bit field is written by hardware by the TCF function
and gives the number of measured Start Stop Oscillator
clock cycles.
7:2
r
Reserved
Read as 0B.
1
rh
Last Message Invalid Notification
This bit indicates if the last received SPI Message was
correctly processed by the device.
0B: Previous Message was processed correctly.
1B: Previous Message was discarded.
0
rh
Parity Bit
Odd Parity Bit.
Datasheet
113
Hardware Description
Rev. 3.1, 2015-07-30
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