1EDI2001AS_15 Datasheet, PDF (45/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Functional Description
2.4.6.3 Disabling the output stage
The output stage of the device can be disabled, i.e. tristated. There are two ways to tristate the device: either via
signal OSD or via the Output Stage Monitor (see Chapter 3.2.4).
The current state of the output stage is indicated by bit SSTAT.HZ. If the bit is cleared, the output stage operates
normally and issues a High or a Low level. If it is set, signals TON and TOFF are tristated.
If the transition from normal operation to tristate is caused by the Output Stage Monitoring, an Event Class A is
generated. If it is caused by a High Level detected on pin OSD, an Event Class A is generated only if bit
SCFG.OSDAD is cleared. Otherwise, if SCFG.OSDAD is set, no event is generated (i.e OPM mode not changed).
When bit SSTAT.HZ is set, sticky bit SER.OSTER is set (independently from the value of SCFG.OSDAD).
Figure 2-16 shows the principle of operation of the Output Stage Disable mechanisms.
The activation of signal NFLTA due to a tristate event depends on the configuration of the chip (see
Chapter 2.4.7).
OSM event
SCFG.OSMD
AND
S
R
OR
SCTRL.OSTC
SSTAT.HZ
OR
OSD Level
CLRS
SCFG.OSDAD
SER.OSTER
S
R
OR
AND
Event Class A
Figure 2-16 Output Stage Disable: Principle of Operation
Note: Bit SSTAT.HZ is the result of the logical operation of bit SCTRL.OSTC being ORed with bit SSTAT2.OSDL.
OSD Signal
The input signal OSD is used as a control signal in order to tristate the output stage of the device. A Low level at
pin OSD corresponds to the normal operation of the device. When signal OSD is at High level, the output stage is
tristated. A High to Low transition of signal OSD clears bit SCTRL.OSTC.
The level read by the device at pin OSD is given by bit SSTAT2.OSDL.
Output Stage Monitoring
The Output Stage Monitoring function is described in Chapter 3.2.4. In case the OSM detects an error condition,
bit SCTRL.OSTC is set and the output stage is tristated.
The functionality of the OSM is controlled by bit SCFG.OSMD. When this bit is set, the OSM is inhibited.
2.4.6.4 Passive Clamping
When the secondary chip is not supplied, signals TOFF, TON and GATE are clamped to V_EE2. See Chapter 5.5.4
for the electrical capability of this feature.
Datasheet
45
Hardware Description
Rev. 3.1, 2015-07-30