1EDI2001AS_15 Datasheet, PDF (81/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Register Description
Primary Error Register
This register provides information on the error status of the device.
PER
Primary Error Register
Offset
03_H
Wakeup Value
n.a.
Reset Value
1C00_H
15
7
VMTO
rh
0
r
6
GER
rh
13
5
OVLO3ER
rh
12
RSTE1
rhs
4
OTER
rh
11
RST1
rhs
3
OSTER
rh
10
ENER
rhs
2
CER1
rhs
9
STPER
rhs
1
LMI
rh
8
SPIER
rhs
0
P
rh
Field
0
RSTE1
RST1
ENER
Bits
15:13
12
11
10
Type
r
rhs
rhs
rhs
Description
Reserved
Read as 0_B.
External Hard Reset Primary Flag
This bit indicates if a reset event has been detected on
the primary chip due to the activation of pin NRST/RDY.
0_B: No external hard reset event has been detected.
1_B: An externally hard reset event has been detected.
This bit is sticky.
Reset Primary Flag
This bit indicates if a reset event has been detected on
the primary chip.
0_B: No reset event has been detected.
1_B: A reset event has been detected.
This bit is sticky.
EN Signal Invalid Flag
This bit indicates if an invalid-to-valid transition on signal
EN has been detected.
0_B: No event has been detected.
1_B: An event has been detected.
This bit is sticky.
Note: This bit can not be cleared while an error condition
is active (bit PSTAT2.ENVAL cleared).
Datasheet
81
Hardware Description
Rev. 3.1, 2015-07-30