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| 1EDI2001AS_15 Datasheet, PDF (112/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step | |||
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Secondary DACLP Activation Configuration Register
This register defines the activation time of signal DACLP.
SACLT
Secondary Active Clamping Configuration Register
Offset
1EH
15
AT
rw
7
0
r
EiceDRIVER⢠SIL
1EDI2001AS
Register Description
Wakeup Value
n.a.
Reset Value
2600H
8
2
1
0
LMI
P
rh
rh
Field
AT
0
LMI
P
Bits
Type Description
15:8
rw
Activation time
This bit field defines the activation time for signal DACLP
(In SSOSC2 clock cycles).
00H: DACLP is at constant High Level.
01H...09H: Reserved.
0AH...FEH: DACLP activation time.
FFH: DACLP is at constant Low Level.
7:2
r
Reserved
Read as 0B.
1
rh
Last Message Invalid Notification
This bit indicates if the last received SPI Message was
correctly processed by the device.
0B: Previous Message was processed correctly.
1B: Previous Message was discarded.
0
rh
Parity Bit
Odd Parity Bit.
Datasheet
112
Hardware Description
Rev. 3.1, 2015-07-30
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