1EDI2001AS_15 Datasheet, PDF (101/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Register Description
Secondary Configuration Register
This register is used to select the configuration of the device.
SCFG
Secondary Configuration Register
Offset
14_H
Wakeup Value
n.a.
Reset Value
0190_H
15
0
r
7
6
5
4
OSDAD
OSMD
Res
VBEC
rw
rw
rwh
rw
11
10
TOSEN
rw
3
2
0
r
9
PSEN
rw
1
LMI
rh
8
DSTCEN
rw
0
P
rh
Field
0
TOSEN
PSEN
DSTCEN
OSDAD
OSMD
Res
Bits
15:11
10
9
8
7
6
5
Type
r
rw
rw
rw
rw
rw
rwh
Description
Reserved
Read as 0_B.
Verification Mode Time Out Duration Selection
This bit selects the duration of the verification mode time
out.
0_B: Regular time-out value (typ. 15 ms).
1_B: Slow time-out value (typ. 60 ms).
Pulse Suppressor Enable Bit
This bit enables the internal pulse suppressor.
0_B: Pulse suppressor is disabled.
1_B: Pulse suppressor is enabled.
DESAT Clamping Enable Bit
This bit enables the internal clamping (to GND2) of the
DESAT pin during PWM OFF commands.
0_B: DESAT clamping is disabled.
1_B: DESAT clamping is enabled.
OSD Event Class A Disable Bit
This bit disables the generation of an Event Class A in
case of an OSD pin Tristate event.
0_B: Event Class A is enabled.
1_B: Event Class A is disabled.
Output Stage Monitoring Disable Bit
This bit disables the internal Output Stage Monitoring
mechanism.
0_B: OSM is working normally.
1_B: OSM is disabled.
Reserved
This bit field is reserved. It should be written with 0_H.
Datasheet
101
Hardware Description
Rev. 3.1, 2015-07-30