1EDI2001AS_15 Datasheet, PDF (21/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Functional Description
2.4.3 PWM Input Stage
The PWM input stage generates from the external signals INP, INSTP and EN the turn-on and turn-off commands
to the secondary side. The general structure of the PWM input block is shown Figure 2-3.
VCC1
INP
INSTP
EN
inhibit _a c t.
en_valid
pwm_cmd
REF0
Figure 2-3 PWM Input Stage
Signals INP, INSTP and EN are pseudo-differential, in the sense that they are not referenced to the common
ground GND1 but to signal REF0. This is intended to make the device more robust against ground bouncing
effects.
Note: Glitches shorter than t_INPR1occurring at signal INP are filtered internally.
Note: Pulses at INP below t_INPPD might be distorted or suppressed.
The 1EDI2001AS supports non-inverted PWM signals only. When a High level on pin INP is detected while signals
INSTP and ENare valid, a turn-on command is issued to the secondary chip. A Low level at pin INP issues a turn-
off command to the secondary chip.
Signal EN can inhibit turn-on commands received at pin INP. A valid signal EN is required in order to have turn-
on commands issued to the secondary chip. If an invalid signal is provided, the PWM input stage issues constantly
turn-off commands to the secondary chip. The functionality of signal ENis detailed in Chapter 2.4.8.
Note: After an invalid-to valid-transition of signal EN, a minimum delay of t_INPEN should be inserted before turning
INP on.
As shown in Figure 2-4, signal INSTP provides a Shoot-Through Protection (STP) to the system. When signal at
pin INSTP is at High level, the internal signal inhibit_act is activated. The inhibition time is defined as the pulse
duration of signal inhibit_act. It corresponds to the pulse duration of signal INSTP to which a minimum dead time
is added. During the inhibition time, rising edges of signal INP are inhibited. Bit PSTAT2.STP is set for the duration
of the inhibition time.
Datasheet
21
Hardware Description
Rev. 3.1, 2015-07-30