1EDI2001AS_15 Datasheet, PDF (48/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Functional Description
Table 2-13 Reset Events Summary
Reset Event
Primary
Secondary
IREF1 shorted to Reset
ground or open
Soft Reset
Memory Error on Reset
Primary
Soft Reset
UVLO2 Event
-
Hard Reset
OSC2 not starting -
at power-up
OSC2 misfunction -
during operation
Hard Reset
Soft Reset
IREF2 open
-
Hard Reset
Notification
(primary)
Notification
(secondary)
• NRST/RDY Low (driven • Bit SER.CER2 set (in
by device during event).
case of lifesign lost).
• Bit PER.RST1 set (once • Output Stage issues a
IREF1 valid again).
PWM OFF command.
• Bit PER.CER1 is not set. • OSD pin functionality
• Event Class B (NFLTB
operational.
activated) at the end of the
reset event.
• NRST/RDY Low (driven • Bit SER.CER2 set (in
by device during event).
case of lifesign lost).
• Bit PER.RST1 set (when • Output Stage issues a
failure condition is
PWM OFF command.
removed).
• OSD pin functionality
• Bit PER.CER1 is not set. operational.
• Event Class B (NFLTB
activated) at the end of the
reset event.
• Event Class B (NFLTB • Signal NUV2 at Low level
activated, bit PER.CER1
(if V_CC2 <V_UVLO2).
set).
• Bit SER.RST2 (once V_CC2
• Bit PSTAT.SRDY cleared valid again).
for the duration of the
• Output Stage issues a
failure.
PWM OFF command.
• OSD pin functionality
operational for: V_CC2 >
V_RST2.
• Event Class B
• Output Stage issues a
(NFLTB activated, bit
PWM OFF command.
PER.CER1 set)
• OSD pin functionality
• Bit PSTAT.SRDY cleared operational.
• Event Class B
• Output Stage issues a
(NFLTB activated, bit
PWM OFF command.
PER.CER1 set)
• OSD pin functionality
• Bit PSTAT.SRDY cleared operational.
for the duration of the
failure.
• Event Class B
None.
(NFLTB activated, bit
PER.CER1 not)
• Bit PSTAT.SRDY cleared
Datasheet
48
Hardware Description
Rev. 3.1, 2015-07-30