1EDI2001AS_15 Datasheet, PDF (73/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Protection and Diagnostics
3.5.9 Internal Clock Supervision
The Primary Clock Supervision functionality is summarized in Table 3-19:
Table 3-19 Primary Clock Supervision Overview
Parameter
Short Description
Function
Supervision of the frequency of OSC1 and SSOSC2.
Periodicity
On Request.
Action in case of event
N.a.
Programmability
No
In-System Testability
No
The clock supervision function consists on the primary clock supervision and the TCF feature.
Primary Clock Supervision
The purpose of this supervision function is to verify the frequency deviation of the primary clock. This function
works in such a way that the PWM input signal is used to start and stop a counter clocked by OSC1. The function
is activated when the device is in OPM5 or OPM6. The counter is incremented for the duration of the High level at
pin INP. At a High-to-Low transition at pin INP, the counter is stopped, and its content is transferred to bit field
PCS.CS1. A plausibility check can therefore be made by the logic. In case of a long INP pulse, the counter does
not overflow but stays at the maximum value until cleared. PCS.CS1 is cleared by setting bit PCTRL.CLRP.
The INP signal is not issued at the output stage.
Note: OSC2 is indirectly monitored by the Life Sign mechanism.
Timing Calibration Feature
The purpose of this supervision function is to measure the frequency of oscillator SSOC2. The PWM input signal
is used to start and stop a counter clocked by SSOSC2. The function is activated when the device is in OPM6
(only). The counter is incremented for the duration of the High level at pin INP. At a High-to-Low transition at pin
INP, the counter is stopped, and its content is transferred to bit field SCS.CS2. A plausibility check can therefore
be made by the logic. In case of a long INP pulse, the counter does not overflow but stays at the maximum value
until cleared. SCS.CS2 is cleared by a reset event only.
The INP signal is not issued at the output stage.
Datasheet
73
Hardware Description
Rev. 3.1, 2015-07-30