1EDI2001AS_15 Datasheet, PDF (28/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

2.4.4.4 SPI Data Integrity Support
EiceDRIVER™ SIL
1EDI2001AS
Functional Description
2.4.4.4.1 Parity Bit
By default, the SPI link relies on an odd parity protection scheme for each transmitted or received 16-bit word of
the SPI message. The parity bit corresponds to the LSB of the 16-bit word. Therefore, the effective payload of a
16-bit word is 15 data bit (plus one parity bit). The parity bit check (on the received data) can be disabled by
clearing bit PCFG.PAREN. In this case, the parity bit is considered as “don’t care”. The generation of the parity bit
by the driver for transmitted words can not be disabled (but can be considered as “don’t care” by the SPI master).
Note: For fixed value commands (ENTER_CMODE, ENTER_VMODE, EXIT_CMODE, NOP), it has to be ensured
that the value of the parity bit is correct even if parity check is disabled. Otherwise, an SPI error will be
generated.
2.4.4.4.2 SPI Error
When the device is not able to process an incoming request message, an SPI error is generated: the received
message is discarded by the driver, bit PER.SPIERis set and the erroneous message is answered with an error
notification (bit LMI set).
Several failures generate an SPI error:
• A parity error is detected on the received word.
• An invalid data word format is received (e.g. not a 16 bit word).
• A word is received, which does not corresponding to a valid Request Message.
• A command is received which can not be processed. For example, the driver receives in Active Mode a
command which is only valid in other operating modes. Another typical example is a read access to the
secondary while the previous read access is not yet completed (device “busy”).
• An SPI access to an invalid address.
Note: the content of a frame with LMI bit set is the value of register PSTAT.
Note: In case of permanent LMI error induced by system failures, it is recommended to apply a reset via pin
NRST/RDY.
Datasheet
28
Hardware Description
Rev. 3.1, 2015-07-30