1EDI2001AS_15 Datasheet, PDF (111/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Register Description
Secondary Second Gate Monitoring Register
This register captures the value of the counter monitoring during the switching sequence.
SGM2
Secondary Second Gate Monitoring Register
Offset
1D_H
Wakeup Value
n.a.
Reset Value
FF01_H
15
7
6
GTCT2
rh
VTOM2
rh
0
r
8
2
1
0
LMI
P
rh
rh
Field
VTOM2
GTCT2
0
LMI
P
Bits
Type Description
15:8
rh
Turn-On Counter Value
This bit field is used to capture the timing of signal GATE
during turn-on sequences. It is cleared at the beginning of
the timing measurement.
7
rh
Gate Timing Capture Trigger 2
This bit indicates the state of the timing capture
mechanism. When it is set, the mechanism is armed. This
bit is cleared at the end of the timing measurement.
Note: In case a new request occurs while the mechanism
is already armed, then this bit is cleared and the
mechanism disarmed.
6:2
r
Reserved
Read as 0_B.
1
rh
Last Message Invalid Notification
This bit indicates if the last received SPI Message was
correctly processed by the device.
0_B: Previous Message was processed correctly.
1_B: Previous Message was discarded.
0
rh
Parity Bit
Odd Parity Bit.
Datasheet
111
Hardware Description
Rev. 3.1, 2015-07-30