1EDI2001AS_15 Datasheet, PDF (25/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2001AS
Functional Description
SCLK
Master _SDO
SDI
NCS
SCLK
SDI ^{Slave 1}
SDO
NCS
SCLK
SDI ^{Slave 2}
SDO
NCS
SCLK
SDI ^{Slave n}
SDO
NCS
Figure 2-7 SPI Daisy Chain Bus Topology
Physical Layer
The SPI interface relies on two shift registers:
• A shift output register, reacting on the rising edges of SCLK.
• A shift input register, reacting on the falling edges of SCLK.
When signal NCS is inactive, the signals at pins SCLK and SDI are ignored. The output SDO is in tristate.
When NCS is activated, the shift output register is updated internally with the value requested by the previous SPI
access.
At each rising edge of the SCLK signal (while NCS is active), the shift output register is serially shifted out by one
bit on the SDO pin (MSB first). At each falling edge of the clock pulse, the data bit available at the input SDI is
latched and serially shifted into the shift input register.
At the deactivation of NCS, the SPI logic checks how many rising and falling edges of the SCLK signal have been
received. In case both counts differ and / or are not a multiple of 16, an SPI Error is generated. The SPI block then
checks the validity of the received 16-bit word. In case of a non valid data, an SPI error is generated. In case no
error is detected, the data is decoded by the internal logic.
The NCS signal is active low.
Input Debouncing Filters
The input stages of signals SDI, SCLK, and NCS include each a Debouncing Filter. The input signals are that way
filtered from glitches and noise.
The input signals SDI and SCLK are analyzed at each edge of the internal clock derived from OSC1. If the same
external signal value is sampled three times consecutively, the signal is considered as valid and is processed by
the SPI logic. Otherwise, the transition is considered as a glitch and is discarded.
Datasheet
25
Hardware Description
Rev. 3.1, 2015-07-30