1EDI2001AS_15 Datasheet, PDF(50/135 Page) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

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1EDI2001AS_15 Datasheet, PDF (50/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

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EiceDRIVERâ¢ SIL

1EDI2001AS

Functional Description

parameters on the primaryand secondary side are protected with a memory protection mechanism. In case the

values are not consistent, a Reset Event and / or an Event Class B is generated.

2.4.10.1.1 Configuration of the SPI Parity Check

The SPI interface supports by default an odd parity check. The Parity Check mechanism (active at the reception

of an SPI word) can be disabled by setting bit PCFG.PAREN to 0B. Setting bit PAREN to 1B enables the Parity

Check.

Parity Bit Generation for the transmitter can not be disabled.

2.4.10.1.2 Configuration of NFLTA Activation in case of Tristate Event

Signal NFLTA is normally activated by a state transition of the internal state machine. However, it can be also

configured to be activated in relation with the primary bits PER.OSTER or PSTAT2.OSTC. This is configured

thanks to bits PCFG.OSTAEN and PCFG.OSMAEN.

2.4.10.1.3 Configuration of the VBE Compensation

The VBE compensation of signal TON and TOFF can be activated or deactivated by writing bit SCFG.VBEC. See

Chapter 2.4.6 for more details.

2.4.10.1.4 Deactivation of Output Stage Monitoring

The OSM function can be disabled by setting bit SCFG.OSMD.

2.4.10.1.5 Deactivation of Events Class A due to pin OSD

By setting bit SCFG.OSDAD, Event Class A are not issued in case of a Tristate event generated by pin OSD. Other

actions such as tristating the output stage or setting bit SER.OSTER are performed normally.

2.4.10.1.6 Clamping of DESAT pin

By setting bit SCFG.DSTCEN, the DESAT signal is clamped to VGND2 while the output stage of the device issues

a PWM OFF command and during blanking time periods. By clearing bit SCFG.DSTCEN, the DESAT clamping is

only activated during blanking time periods.

2.4.10.1.7 Activation of the Pulse Suppressor

The pulse suppressor function associated with the TTOFF function can be activated by setting bit SCFG.PSEN.

When activated, SRTTOF.RTVAL shall be programmed with a minimum value (see Page 108).

2.4.10.1.8 Configuration of the Verification Mode Time Out Duration

The duration of the time out in verification mode is selectable via bit SCFG.TOSEN.

Datasheet

Hardware Description

Rev. 3.1, 2015-07-30

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