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1EDI2001AS_15 Datasheet, PDF (103/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step
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EiceDRIVER™ SIL
1EDI2001AS
Register Description
Secondary Control Register
This register is used to control the device during run-time.
SCTRL
Secondary Control Register
Offset
16H
Wakeup Value
n.a.
Reset Value
00F1H
15
13
12
11
10
9
8
0
OSTC
CLRS
0
GPONS
r
7
rhs
rh
rh
4
3
2
rh
1
0
GPOFS
0
LMI
P
rh
r
rh
rh
Field
0
OSTC
CLRS
0
GPONS
GPOFS
0
LMI
Datasheet
Hardware Description
Bits
15:13
12
11
10
9:8
7:4
3:2
1
Type
r
rhs
rh
rh
rh
rh
r
rh
Description
Reserved
Read as 0B.
Output Stage Tristate Control
This bit is used by the hardware to control the state of the
output stage.This bit is set in case of an OSM event. It is
cleared by either a falling edge on pin OSD or when bit
PCTRL.CLRS is set.
Clear Secondary Request Bit
This bit is set by writing PCTRL.CLRS.
Reserved
Read as 0B.
Gate Turn-On Plateau Level Configuration
This bit field indicates the current configuration of the
plateau level for WTO. Coding is identical to
PCTRL.GPON.
Note: This bit field is a mirror of PSTAT.GPONS.
Gate Turn-Off Plateau Level Configuration (regular
turn-off)
This bit field indicates the current configuration of the
TTOFF plateau level (for regular turn-off). Coding is
identical to PCTRL2.GPOF.
Note: This bit field is a mirror of PSTAT.GPOFS.
Reserved
Read as 0B.
Last Message Invalid Notification
This bit indicates if the last received SPI Message was
correctly processed by the device.
0B: Previous Message was processed correctly.
1B: Previous Message was discarded.
103
Rev. 3.1, 2015-07-30
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