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| 1EDI2001AS_15 Datasheet, PDF (79/135 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step | |||
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EiceDRIVER⢠SIL
1EDI2001AS
Register Description
Primary Second Status Register
This register contains information on the status of the device.
PSTAT2
Primary Second Status Register
Offset
02H
Wakeup Value
n.a.
Reset Value
0010H
15
12
11
10
9
8
0
OSTC
STP
OT
HZ
r
rh
rh
rh
rh
7
5
4
3
2
1
0
OPM
FLTB
FLTA
ENVAL
LMI
P
rh
rhs
rhs
rh
rh
rh
Field
0
OSTC
STP
OT
HZ
Bits
15:12
11
10
9
8
Type
r
rh
rh
rh
rh
Description
Reserved
Read as 0B.
Output Stage Tristate Control
This bit is set in case an OSM event.
Note: This bit is a mirror of bit SCTRL.OSTC
Shoot Through Protection Status
This bit is set in case the shoot through protection
inhibition time (i.e. would inhibit a PWM rising edge).
0B: STP inhibition is not active.
1B: STP inhibition is active.
Over Temperature Status
This bit is set in case an overtemperature condition is
detected.
0B: The device is in normal operation.
1B: The device is in overtemperature condition.
Note: This bit is a mirror of bit SSTAT.OT
Tristate Output Stage Status
This bit is set in case the output stage is in tristate.
0B: The output stage is in normal operation.
1B: The output stage is tristated.
Note: This bit is a mirror of bit SSTAT.HZ
Datasheet
79
Hardware Description
Rev. 3.1, 2015-07-30
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