MC68HC711D3_05 Datasheet, PDF (99/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Real-Time Interrupt
PR1 and PR0 — Timer Prescaler Select Bits
Refer to Table 8-4.
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2
enable the corresponding interrupt sources.
8.5.2 Timer Interrupt Flag 2 Register
Bits of the timer interrupt flag 2 register (TFLG2) indicate the occurrence of timer system events. Coupled
with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either
a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Address: $0025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOF
RTIF PAOVF PAIF
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 8-17. Timer Interrupt Flag 2 Register (TFLG2)
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to 1 at the end of every RTI period. To clear RTIF, write a byte
to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 8.7 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 8.7 Pulse Accumulator.
Bits 3–0 — Not implemented
Always read 0.
8.5.3 Pulse Accumulator Control Register
Bits RTR1 and RTR0 of the pulse accumulator control register (PACTL) select the rate for the real-time
interrupt system. Bit DDRA3 determines whether port A bit three is an input or an output when used for
general-purpose I/O. The remaining bits control the pulse accumulator.
Address: $0026
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRA7
Write:
PAEN PAMOD PEDGE DDRA3
I4/O5
RTR1
RTR0
Reset: 0
0
0
0
0
0
0
0
Figure 8-18. Pulse Accumulator Control Register (PACTL)
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
99