MC68HC711D3_05 Datasheet, PDF (73/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

SCI Registers
SCP1 and SCP0 — SCI Baud Rate Prescaler Select Bits
These two bits select a prescale factor for the SCI baud rate generator that determines the highest
possible baud rate.
Table 6-1. Baud Rate Prescale Selects
SCP1
and SCP0
00
01
10
11
Divide
Internal Clock
By
1
3
4
13
4.0 MHz
(Baud)
62.50 K
20.83 K
15.625 K
4800
Crystal Frequency in MHz
8.0 MHz
(Baud)
10.0 MHz
(Baud)
125.0 K 156.25 K
41.67 K
52.08 K
31.25 K
38.4 K
9600
12.02 K
12.0 MHz
(Baud)
187.5 K
62.5 K
46.88 K
14.42 K
SCR2–SCR0 — SCI Baud Rate Select Bits
These three bits select receiver and transmitter bit rate based on output from baud rate prescaler
stage.
Table 6-2. Baud Rate Selects
SCR2–SCR0
000
001
010
011
100
101
110
111
Divide
Prescaler
By
1
2
4
8
16
32
64
128
Highest Baud Rate
(Prescaler Output from Table 6-1)
4800
9600
38.4 K
4800
9600
38.4 K
2400
4800
19.2 K
1200
2400
9600
600
1200
4800
300
600
2400
150
300
1200
—
150
600
—
—
300
The prescale bits, SCP1 and SCP0, determine the highest baud rate and the SCR2–SCR0 bits select
an additional binary submultiple (÷1, ÷2, ÷4, through ÷128) of this highest baud rate. The result of these
two dividers in series is the 16 X receiver baud rate clock. The SCR2–SCR0 bits are not affected by
reset and can be changed at any time, although they should not be changed when any SCI transfer is
in progress.
Figure 6-8 illustrates the SCI baud rate timing chain. The prescale select bits determine the highest
baud rate. The rate select bits determine additional divide by two stages to arrive at the receiver timing
(RT) clock rate. The baud rate clock is the result of dividing the RT clock by 16.
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
73