MC68HC711D3_05 Datasheet, PDF (43/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Instruction Set
Table 3-2. Instruction Set (Sheet 5 of 8)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Condition Codes
Opcode Operand Cycles S X H I N Z V C
INX
Increment
IX + 1 ⇒ IX
INH
Index Register
X
08
—
3
————— ∆ ——
INY
Increment
IY + 1 ⇒ IY
Index Register
Y
INH
18
08
—
4
————— ∆ ——
JMP (opr)
Jump
See Figure 3-2
EXT
IND,X
IND,Y 18
7E hh ll
6E ff
6E ff
3
————————
3
4
JSR (opr)
Jump to
Subroutine
See Figure 3-2
DIR
EXT
IND,X
IND,Y 18
9D dd
BD hh ll
AD ff
AD ff
5
————————
6
6
7
LDAA (opr)
Load
Accumulator
A
M⇒A
A
IMM
86 ii
A
DIR
96 dd
A
EXT
B6 hh ll
A
IND,X
A6 ff
A
IND,Y 18
A6 ff
2
———— ∆ ∆ 0 —
3
4
4
5
LDAB (opr)
Load
Accumulator
B
M⇒B
B
IMM
C6 ii
B
DIR
D6 dd
B
EXT
F6 hh ll
B
IND,X
E6 ff
B
IND,Y 18
E6 ff
2
———— ∆ ∆ 0 —
3
4
4
5
LDD (opr)
Load Double
Accumulator
D
M ⇒ A,M + 1 ⇒ B
IMM
DIR
EXT
IND,X
IND,Y 18
CC jj kk
DC dd
FC hh ll
EC ff
EC ff
3
———— ∆ ∆ 0 —
4
5
5
6
LDS (opr)
Load Stack
Pointer
M : M + 1 ⇒ SP
IMM
DIR
EXT
IND,X
IND,Y 18
8E jj kk
9E dd
BE hh ll
AE ff
AE ff
3
———— ∆ ∆ 0 —
4
5
5
6
LDX (opr)
Load Index
Register
X
M : M + 1 ⇒ IX
IMM
CE jj kk
DIR
DE dd
EXT
FE hh ll
IND,X
EE ff
IND,Y CD EE ff
3
———— ∆ ∆ 0 —
4
5
5
6
LDY (opr)
Load Index
Register
Y
M : M + 1 ⇒ IY
IMM
18
DIR
18
EXT
18
IND,X 1A
IND,Y 18
CE jj kk
DE dd
FE hh ll
EE ff
EE ff
4
———— ∆ ∆ 0 —
5
6
6
6
LSL (opr)
LSLA
LSLB
LSLD
Logical Shift
Left
Logical Shift
Left A
Logical Shift
Left B
Logical Shift
Left Double
C b7
C b7
C b7
0
b0
A
0
b0
B
0
b0
0
C b7 A b0 b7 B b0
EXT
IND,X
IND,Y 18
INH
78 hh ll
68 ff
68 ff
48
—
INH
58
—
INH
05
—
6
———— ∆ ∆ ∆ ∆
6
7
2
———— ∆ ∆ ∆ ∆
2
———— ∆ ∆ ∆ ∆
3
———— ∆ ∆ ∆ ∆
LSR (opr)
LSRA
LSRB
Logical Shift
Right
Logical Shift
Right A
Logical Shift
Right B
0
b7
0
b7
0
b7
b0 C
A
b0 C
B
b0 C
EXT
IND,X
IND,Y 18
INH
74 hh ll
64 ff
64 ff
44
—
INH
54
—
6
———— 0 ∆ ∆ ∆
6
7
2
———— 0 ∆ ∆ ∆
2
———— 0 ∆ ∆ ∆
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
43