MC68HC711D3_05 Datasheet, PDF (28/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Operating Modes and Memory
Addr.
Register Name
Bit 7
$0026
Pulse Accumulator Control ^Read:
Register (PACTL) Write:
See pages 99 and 102. _Reset:
DDRA7
0
Pulse Accumulator Count Register ^Read: _{Bit 7}
$0027
(PACNT) Write:
See page 103. _Reset:
$0028
SPI Control Register ^Read: _SPIE
(SPCR) Write:
See page 81. _{Reset: 0}
$0029
SPI Status Register ^Read: _SPIF
(SPSR) Write:
See page 82. _{Reset: 0}
$002A
SPI Data I/O Register ^Read: _{Bit 7}
(SPDR) Write:
See page 83. _Reset:
$002B
Baud Rate Register ^Read:
(BAUD) Write:
See page 72. _Reset:
TCLR
0
$002C
SCI Control Register 1 ^Read: _R8
(SCCR1) Write:
See page 70. _{Reset: U}
$002D
SCI Control Register 2 ^Read: _TIE
(SCCR2) Write:
See page 70. _{Reset: 0}
$002E
SCI Status Register Read:
(SCSR) _Write:
See page 71.
Reset:
TDRE
1
$002F
SCI Data Register ^Read:
(SCDR) Write:
See page 69. _Reset:
R7/T7
$0030
↓
$0038
Reserved
R
6
5
4
3
PAEN PAMOD PEDGE DDRA3
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Unaffected by reset
SPE DWOM MSTR CPOL
0
0
0
0
WCOL
0
MODF
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Unaffected by reset
0
SCP1 SCP0 RCKB
0
0
0
0
T8
0
M
WAKE
U
0
0
0
TCIE
RIE
ILIE
TE
0
0
0
0
TC
RDRF IDLE
OR
1
0
0
0
R6/T6 R5/T5 R4/T4 R3/T3
Unaffected by reset
R
R
R
R
2
I4/O5
0
Bit 2
CPHA
1
0
0
Bit 2
SCR2
U
0
0
RE
0
NF
0
R2/T2
R
1
RTR1
0
Bit 1
SPR1
U
0
0
Bit 1
SCR1
U
0
0
RWU
0
FE
0
R1/T1
R
Bit 0
RTR0
0
Bit 0
SPR0
U
0
0
Bit 0
SCR0
U
0
0
SBK
0
0
0
R0/T0
R
$0039
System Configuration Options ^Read:
0
Register (OPTION) Write:
See page 49. _{Reset: 0}
0
IRQE
DLY
CME
0
CR1
CR0
0
0
1
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Register and Control Bit Assignments (Sheet 4 of 5)
MC68HC711D3 Data Sheet, Rev. 2.1
28
Freescale Semiconductor