MC68HC711D3_05 Datasheet, PDF (114/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Electrical Characteristics
9.7 Peripheral Port Timing
Characteristic⁽¹⁾
Symbol
1.0 MHz
Min Max
2.0 MHz
Min Max
3.0 MHz
Unit
Min Max
Frequency of operation (E-clock frequency)
f_O
1.0 1.0 2.0 2.0 3.0 3.0 MHz
E-clock period
t_CYC
1000 —
500
—
333
—
ns
Peripheral data setup time⁽²⁾
MCU read of ports A, B, C, and D
t_PDSU
100 —
100
—
100
—
ns
Peripheral data hold time⁽²⁾
MCU read of ports A, B, C, and D
t_PDH
50
—
50
—
50
— ns
Delay time, peripheral data write
MCU write to port A
MCU writes to ports B, C, and D
t_PWD = 1/4 t_cyc + 150 ns
t_PWD
— 200 — 200 — 200
ns
— 350 — 225 — 183
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H. All timing is shown with respect to 20% V_DD and 70% V_DD, unless
otherwise noted.
2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively).
E
PORTS
B, C, D
PORT A
E
PORTS
A, B, C, D
MCU WRITE TO PORT
PREVIOUS PORT DATA
t _PWD
PREVIOUS PORT DATA
NEW DATA VALID
tPWD
NEW DATA VALID
Figure 9-8. Port Write Timing Diagram
MCU READ OF PORT
tPDSU
tPDH
Figure 9-9. Port Read Timing Diagram
MC68HC711D3 Data Sheet, Rev. 2.1
114
Freescale Semiconductor