MC68HC711D3_05 Datasheet, PDF (115/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

9.8 Expansion Bus Timing
Expansion Bus Timing
Num
Characteristic⁽¹⁾
Frequency of operation (E-clock frequency)
1 Cycle time
2 Pulse width, E low, PW_EL = 1/2 t_cyc — 23 ns
3 Pulse width, E high, PW_EH = 1/2 t_cyc – 28 ns
4A E and AS rise time
4B E and AS fall time
9 Address hold time^(2)a, t_AH = 1/8 t_cyc – 29.5 ns
Non-muxed address valid time to E rise
12
t_AV = PW_EL – (t_ASD + 80 ns)^(2)a
17 Read data setup time
18 Read data hold time (max = t_MAD)
19 Write data delay time, t_DDW = 1/8 t_cyc + 65.5 ns^(2)a
21 Write data hold time, t_DHW = 1/8 t_cyc – 29.5 ns^(2)a
Muxed address valid time to E rise
22
t_AVM = PW_EL – (t_ASD + 90 ns)^(2)a
Muxed address valid time to AS fall
24 _{tASL = PWASH – 70 ns}
25 Muxed address hold time, t_AHL = 1/8 t_cyc – 29.5 ns^(2)b
26 Delay time, E to AS rise, t_ASD = 1/8 t_cyc – 9.5 ns^(2)a
27 Pulse width, AS high, PW_ASH = 1/4 t_cyc – 29 ns
28 Delay time, AS to E rise, t_ASED = 1/8 t_cyc – 9.5 ns^(2)b
29 ^{MPU address access time(2)a}
t_ACCA = t_cyc – (PW_EL– t_AVM) – t_DSR – t_f
35 MPU access time , t_ACCE = PW_EH – t_DSR
Muxed address delay (previous cycle MPU read)
36
t_MAD = t_ASD + 30 ns^(2)a(3)
Symbol
f_O
t_cyc
PW_EL
PW_EH
t_r
t_f
t_AH
1.0 MHz
Min Max
dc 1.0
1000 —
477 —
472 —
— 20
— 20
95.5 —
2.0 MHz 3.0 MHz
Unit
Min Max Min Max
dc 2.0 dc 3.0 MHz
500 — 333 — ns
227 — 146 — ns
222 — 141 — ns
— 20 — 20 ns
— 20 — 15 ns
33 — 26 — ns
t_AV 281.5 — 94 — 54 — ns
t_DSR
t_DHR
t_DDW
t_DHW
30 — 30 — 30 — ns
0 145.5 0 83 0 51 ns
— 190.5 — 128 — 71 ns
95.5 — 33 — 26 — ns
t_AVM 271.5 — 84 — 54 — ns
t_ASL 151 — 26 — 13 — ns
t_AHL 95.5 — 33 — 31 — ns
t_ASD 115.5 — 53 — 31 — ns
PW_ASH 221 — 96 — 63 — ns
t_ASED 115.5 — 53 — 31 — ns
t_ACCA 744.5 — 307 — 196 — ns
t_ACCE — 442 — 192 — 111 ns
t_MAD 145.5 — 83 — 51 — ns
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H. All timing is shown with respect to 20% V_DD and 70% V_DD, unless
otherwise noted.
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 t_CYC in the above formulas, where applicable:
(a) (1-dc) × 1/4 t_CYC
(b) dc × 1/4 t_CYC
Where:
DC is the decimal value of duty cycle percentage (high time).
3. Formula only for dc to 2 MHz.
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
115