MC68HC711D3_05 Datasheet, PDF (97/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Output Compare (OC)
PR1 and PR0 — Timer Prescaler Select Bits
These bits are used to select the prescaler divide-by ratio. In normal modes, PR1 and PR0 can be
written once only, and the write must be within 64 cycles after reset. Refer to Table 8-4 for specific
timing values.
Table 8-4. Timer Prescale
PR1 and PR0
00
01
10
11
Prescaler
1
4
8
16
8.4.10 Timer Interrupt Flag 2 Register
The timer interrupt flag 2 register (TFLG2) bits indicate when certain timer system events have occurred.
Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same
position.
Address: $0025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOF
RTIF PAOVF PAIF
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 8-15. Timer Interrupt Flag 2 Register (TFLG2)
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
Refer to 8.5 Real-Time Interrupt.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 8.7 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 8.7 Pulse Accumulator.
Bits 3–0 — Not implemented
Always read 0.
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
97