MC68HC711D3_05 Datasheet, PDF (40/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Central Processor Unit (CPU)
Table 3-2. Instruction Set (Sheet 2 of 8)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Condition Codes
Opcode Operand Cycles S X H I N Z V C
ADDB (opr) Add Memory to
B
B+M⇒B
B
IMM
CB ii
B
DIR
DB dd
B
EXT
FB hh ll
B
IND,X
EB ff
B
IND,Y 18
EB ff
2
—— ∆ — ∆ ∆ ∆ ∆
3
4
4
5
ADDD (opr) Add 16-Bit to D D + (M : M + 1) ⇒ D
IMM
DIR
EXT
IND,X
IND,Y 18
C3 jj kk
D3 dd
F3 hh ll
E3 ff
E3 ff
4
———— ∆ ∆ ∆ ∆
5
6
6
7
ANDA (opr)
AND A with
Memory
A•M⇒A
A
IMM
84 ii
A
DIR
94 dd
A
EXT
B4 hh ll
A
IND,X
A4 ff
A
IND,Y 18
A4 ff
2
———— ∆ ∆ 0 —
3
4
4
5
ANDB (opr)
AND B with
Memory
B•M⇒B
B
IMM
C4 ii
B
DIR
D4 dd
B
EXT
F4 hh ll
B
IND,X
E4 ff
B
IND,Y 18
E4 ff
2
———— ∆ ∆ 0 —
3
4
4
5
ASL (opr) Arithmetic Shift
Left
0
C b7
b0
EXT
IND,X
IND,Y 18
78 hh ll
68 ff
68 ff
6
———— ∆ ∆ ∆ ∆
6
7
ASLA
Arithmetic Shift
A
INH
Left A
C b7
0
b0
48
—
2
———— ∆ ∆ ∆ ∆
ASLB
Arithmetic Shift
B
INH
Left B
C b7
0
b0
58
—
2
———— ∆ ∆ ∆ ∆
ASLD
Arithmetic Shift
INH
Left D
0
C b7 A b0 b7 B b0
05
—
3
———— ∆ ∆ ∆ ∆
ASR
Arithmetic Shift
Right
b7
b0 C
EXT
IND,X
IND,Y 18
77 hh ll
67 ff
67 ff
6
———— ∆ ∆ ∆ ∆
6
7
ASRA
Arithmetic Shift
Right A
A
INH
b7
b0 C
ASRB
Arithmetic Shift
Right B
B
INH
b7
b0 C
47
—
57
—
2
———— ∆ ∆ ∆ ∆
2
———— ∆ ∆ ∆ ∆
BCC (rel)
Branch if Carry
Clear
?C=0
REL
24 rr
3
————————
BCLR (opr)
(msk)
Clear Bit(s)
M • (mm) ⇒ M
DIR
IND,X
IND,Y 18
15 dd mm
1D ff mm
1D ff mm
6
———— ∆ ∆ 0 —
7
8
BCS (rel)
Branch if Carry
Set
?C=1
REL
25 rr
3
————————
BEQ (rel) Branch if = Zero
?Z=1
REL
27 rr
3
————————
BGE (rel) Branch if ∆ Zero
?N⊕V=0
REL
2C rr
3
————————
BGT (rel) Branch if > Zero ? Z + (N ⊕ V) = 0
REL
2E rr
3
————————
BHI (rel)
Branch if
?C+Z=0
REL
22 rr
3
————————
Higher
BHS (rel)
Branch if
Higher or Same
?C=0
REL
24 rr
3
————————
BITA (opr)
Bit(s) Test A
with Memory
A•M
A
IMM
85 ii
A
DIR
95 dd
A
EXT
B5 hh ll
A
IND,X
A5 ff
A
IND,Y 18
A5 ff
2
———— ∆ ∆ 0 —
3
4
4
5
MC68HC711D3 Data Sheet, Rev. 2.1
40
Freescale Semiconductor