MC68HC711D3_05 Datasheet, PDF (71/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

SCI Registers
ILIE — Idle Line Interrupt Enable Bit
1 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE — Transmitter Enable Bit
When TE goes from 0 to 1, one unit of idle character time (logic 1) is queued as a preamble.
0 = Transmitter disabled
1 = Transmitter enabled
RE — Receiver Enable Bit
0 = Receiver disabled
1 = Receiver enabled
RWU — Receiver Wakeup Control Bit
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
SBK — Send Break Bit
At least one character time of break is queued and sent each time SBK is written to 1. More than one
break may be sent if the transmitter is idle at the time the SBK bit is toggled on and off, as the baud
rate clock edge could occur between writing the 1 and writing the 0 to SBK.
0 = Break generator off
1 = Break codes generated as long as SBK = 1
6.7.4 SCI Status Register
The SCI status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI
system interrupt.
Address: $002E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
Write:
Reset: 1
1
0
0
0
0
0
0
Figure 6-6. SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then
writing to SCDR.
0 = SCDR busy
1 = SCDR empty
TC — Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress).
Clear the TC flag by reading SCSR with TC set and then writing to SCDR.
0 = Transmitter busy
1 = Transmitter idle
RDRF — Receive Data Register Full Flag
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR with RDRF set and then reading SCDR.
0 = SCDR empty
1 = SCDR full
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
71