MC68HC711D3_05 Datasheet, PDF (102/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmable Timer
8.7.1 Pulse Accumulator Control Register
Four of the pulse accumulator control register (PACTL) bits control an 8-bit pulse accumulator system.
Another bit enables either the OC5 function or the IC4 function, while two other bits select the rate for the
real-time interrupt system.
Address: $0026
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRA7
Write:
PAEN PAMOD PEDGE DDRA3
I4/O5
RTR1
RTR0
Reset: 0
0
0
0
0
0
0
0
Figure 8-20. Pulse Accumulator Control Register (PACTL)
DDRA7 — Data Direction Control for Port A Bit 7
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used as
general-purpose I/O or as an output compare.
NOTE
Even when port A bit 7 is configured as an output, the pin still drives the
input to the pulse accumulator.
Refer to Chapter 5 Input/Output (I/O) Ports for more information.
PAEN — Pulse Accumulator System Enable Bit
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode Bit
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control Bit
This bit has different meanings depending on the state of the PAMOD bit, as shown in Table 8-8.
Table 8-8. Pulse Accumulator Edge Control
PAMOD
0
0
1
1
PEDGE
Action on Clock
0 PAI falling edge increments the counter.
1 PAI rising edge increments the counter.
0 A 0 on PAI inhibits counting.
1 A 1 on PAI inhibits counting.
DDRA3 — Data Direction Register for Port A Bit 3
Refer to Chapter 5 Input/Output (I/O) Ports.
I4/O5 — Input Capture 4/Output Compare 5 Bit
Refer to 8.3 Input Capture.
RTR1 and RTR0 — RTI Interrupt Rate Select Bits
Refer to 8.5 Real-Time Interrupt.
MC68HC711D3 Data Sheet, Rev. 2.1
102
Freescale Semiconductor